Field of the Invention
The present invention relates to an integrated memory having memory cells and buffer capacitors. Integrated memories, such as those referred to as DRAM memories, for example, usually have memory cells each containing a selector transistor and a storage capacitor. The storage capacitors thereof are each connected through a respective selector transistor to one of a plurality of column lines of a matrix-shaped memory cell array. Control terminals of the respective selector transistors are each connected to one of a plurality of row lines, through which the memory cells can be selected.
In addition, such memories often have so-called buffer capacitors for stabilizing a voltage supply on the memory chip. They serve, in particular, to filter voltage peaks and thus ensure a certain level of dielectric strength of the memory. In the interest of largely homogeneous area coverage on the memory chip, buffer capacitors are frequently constructed and disposed in a similar way to the memory cells or their storage capacitors. This means that in that case the buffer capacitors also have a respectively assigned selector transistor. In such a case they are usually disposed in a region of the periphery of the memory chip. That region also has a structure similar to the memory cell array, for reasons of homogeneous area coverage. A homogeneous area coverage on the memory chip provides, in particular, advantages for the manufacture of the chip, for example improved planarization properties.
In order to activate the buffer capacitors permanently, the corresponding selector transistor is to be switched on permanently. Since the selector transistors generally age more quickly when permanently loaded, and as a result can become faulty more quickly than the buffer capacitors, their operational capability can thus be adversely affected relatively quickly. Furthermore, short circuits can occur in the selector transistors between their respective control terminals and their controlled paths. Those short circuits can arise, for example, due to inconsistent or faulty fabrication processes. If a selector transistor has a short circuit, the operational capability of the associated buffer capacitor is thus also adversely affected. The dielectric strength of the memory chip as a whole is thus adversely affected since generally no corresponding redundancy is provided for the buffer capacitors in such memory chips.
It is accordingly an object of the invention to provide an integrated memory having memory cells and buffer capacitors, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type, which has largely homogeneous area coverage and in which a comparatively high dielectric strength can be produced permanently through the use of the buffer capacitors.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising a plurality of column lines and a plurality of row lines. Memory cells each have a selector transistor and a storage capacitor connected through the selector transistor to one of the column lines. The selector transistor has a control terminal connected to one of the row lines. Contacts are each connected to another of the column lines. Buffer capacitors are disposed in such a way that connections between a respective one of the buffer capacitors and one of the contacts are each disposed parallel to another of the row lines.
The buffer capacitors are disposed, for example, in a region of the periphery of the memory chip. In the interest of homogeneous area coverage, this region has a structure similar to a memory cell array in which the memory cells are located. This means that this region also has column lines and row lines, with the buffer capacitors each being connected to a contact to one of these column lines. The column lines are connected, for example, to a terminal for a first potential of a voltage supply, and the respective buffer capacitors are connected to a terminal for a second potential of the voltage supply. This means that the buffer capacitors serve to equalize voltage peaks between the first potential and the second potential of the voltage supply.
Since both the memory cell array in which the memory cells are disposed and the region in which the buffer capacitors are disposed have column lines and row lines, largely homogeneous area coverage is ensured. The row lines and column lines of the memory cell array serve to select or to read or to write to the memory cells, the column lines and row lines in the region in which the buffer capacitors are disposed and serve to produce a necessary dielectric strength of the memory chip.
The connection between the respective buffer capacitor and the contact to the respective column line is to he produced parallel to one of the row lines. By virtue of this fact, when the memory chip is manufactured, a diffusion series resistor can be produced between the respective buffer capacitor and the contact. This means that the respective buffer capacitor and the contact are not connected to one another through a selector transistor. This results, in particular, in the advantage that as a result of the absence of the selector transistor, the error mechanisms of such a transistor also cannot influence the operational capability of the buffer capacitors. This ensures a comparatively high dielectric strength of the memory chip as a result of the buffer capacitors.
A further advantage of the invention is that the respective row lines do not have to be operated in a (permanently) active state to select the corresponding buffer capacitors. Since the respective row lines do not perform any selection function with respect to the buffer capacitors, those row lines can be connected to the same potential as the column lines connected to the buffer capacitors. As a result, those row lines and column lines are at the same potential. Therefore, no leakage current occurs if there is a short circuit between the respective lines.
According to one advantageous embodiment of the invention, the buffer capacitors have an identical geometric structure to the storage capacitors. In addition to largely homogenizing area coverage, this also simplifies the manufacturing process because only one type or structure of capacitor is provided, for example in the form of a trench capacitor.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having memory cells and buffer capacitors, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.